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Grammatikakis Miltos D., Coppola Marcello, Locatelli Riccardo, Maruccia Giuseppe, Pieralisi Lorenzo:
Design Of Cost-Efficient Interconnect Processing Units

The Spidergon Stnoc

Series editor: FarhadMafie

Taylor & Francis Ltd (United States), 2008
Hardback, 288 pages
Size: 236x163 mm
ISBN: 9781420044713
ISBN-10: 1420044710

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Design Of Cost-Efficient Interconnect Processing Units

Examines the technology that is set to replace well-known shared bus architectures, such as STBus, for demanding multiprocessor system-on-chip (SoC) applications. This book shows how the System-on-Chip and Network-on-Chip technology works why developers designed it the way they did the system-level design methodology.

Related links:

Miltos D. Grammatikakis
Marcello Coppola
Riccardo Locatelli
Giuseppe Maruccia
Lorenzo Pieralisi
Farhad Mafie
Circuits & components
Electronics engineering
Electronics & communications engineering
Technology, engineering, agriculture, veterinary science
Taylor & Francis Ltd

More information from Wikipedia:

Miltos D. Grammatikakis
Marcello Coppola
Riccardo Locatelli
Giuseppe Maruccia
Lorenzo Pieralisi
Farhad Mafie
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