Wang Laung-Terng, Stroud Charles E., Touba Nur:
System-On-Chip Test Architectures
Nanometer Design For Testability
Elsevier Science & Technology (United States), 2008
Hardback, 896 pages
Size: 235x191 mm
ISBN: 9780123739735
ISBN-10: 012373973X
List price: £39.99
You save: 15%
System-On-Chip Test Architectures
A guide to VLSI Testing and Design-for-Testability techniques that allows students, researchers, DFT practitioners, and VLSI designers to master System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. It also includes practical problems at the end of each chapter for students.

