Wang Laung-Terng, Stroud Charles E., Touba Nur:
System-On-Chip Test Architectures

Nanometer Design For Testability

Elsevier Science & Technology (United States), 2008
Hardback, 896 pages
Size: 235x191 mm
ISBN: 9780123739735
ISBN-10: 012373973X

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System-On-Chip Test Architectures

A guide to VLSI Testing and Design-for-Testability techniques that allows students, researchers, DFT practitioners, and VLSI designers to master System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. It also includes practical problems at the end of each chapter for students.

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Laung-Terng Wang
Charles E. Stroud
Nur Touba
Electrical engineering
Energy technology & engineering
Technology, engineering, agriculture, veterinary science
Elsevier Science & Technology

More information from Wikipedia:

Laung-Terng Wang
Charles E. Stroud
Nur Touba
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